1. Field of the Invention
The present invention relates to a frequency multiplier, and particularly to a frequency multiplier for multiplying the frequency of an input signal by utilizing one or more delay circuits and an exclusive logic circuit.
2. Description of the Prior Art
FIG. 1 is a circuit diagram illustrating the arrangement of a conventional frequency multiplier of this kind, in which input clock signal 300 and an output of delay circuit 302 for delaying signal 300 are utilized to obtain output clock signal 303 whose frequency is doubled by means of exclusive OR circuit 301.
The duty factor (the ratio of the H level period of time of output clock signal 303 to its single cycle time) of output clock signal 303 for the above frequency multiplier is determined by the delay time of the delay circuit.
FIG. 2 is a timing chart illustrating the relationship between input clock signal 300, the output signal of delay circuit 302 and output clock signal 303. In order to set the duty factor of output clock signal 303 to 50%, as shown in the same figure, assuming that the cycle and the duty factor of input clock signal 300 are T.sub.i and 50%, respectively, it is necessary to set delay time T.sub.D of delay circuit 302 to T.sub.D =T.sub.i /4.
However, if this delay circuit is arranged with a semiconductor integrated circuit, then, as shown in Table 1, depending on power voltage V.sub.DD, ambient temperature T.sub.a and the manufacturing condition of the transistor (threshold voltage: V.sub.TP, V.sub.TN), delay time T.sub.D causes errors of approximately -50% to +100% relative to its design value.
Accordingly, if the frequency multiplier is designed with the circuit arrangement of FIG. 1, then the duty factor of the waveform of the output clock signal is changed as shown in FIGS. 3 and 4.
FIG. 3 shows an output waveform when delay time T.sub.D changes by -50%, and FIG. 4 shows an output waveform when the delay time changes by +50%. If delay time T.sub.D changes by +100%, the output waveform remains fixed to the high level.
Therefore, if such an output clock signal is externally used, then a drawback results in that the multiplier malfunctions due to the fluctuation of the duty factor.